Senior Formal Verification Engineer
--10xEngineers--
Location: Lahore, on-site
Job Type: Full-time
Industry: Semiconductor, Formal Verification
Job Summary
For years, you have been an architect of silicon, whether crafting complex RTL or developing the sophisticated environments that test it. You understand how hardware lives and breathes. But have you ever wondered how to prove, beyond any shadow of a doubt, that a design can never fail?
At 10xEngineers, we are looking for seasoned Senior Digital Hardware Engineers, including RTL Designers, Verification Engineers (DV), and Architects to make a high-impact transition into the world of Formal Property Verification (FPV). We recognize that the fundamental DNA of a great Formal Engineer is rooted in a deep mastery of microarchitecture and a rigorous engineering mindset, regardless of your previous specific functional role.
This is not just a job change; it is an invitation to evolve your hardware expertise from traditional methodologies to exhaustive mathematical proof. You will join an elite group of engineers in Lahore working on cutting-edge silicon, shifting your focus to mathematically proving the integrity of complex systems. If you have the microarchitectural expertise, we have the roadmap to turn you into a Formal Verification expert.
What you’ll do
Develop and execute formal verification test plans for complex processor cores and SoC IPs.
Build and maintain SystemVerilog Assertions (SVA) based formal verification environments.
Model complex microarchitectural behaviors and write assumptions to bound state spaces accurately.
Collaborate with design and verification teams to ensure mathematically exhaustive coverage.
Utilize advanced formal methodologies (abstractions, path-decomposition) and tools like JasperGold and VC Formal to manage state-space explosion and resolve design issues.
Participate in microarchitecture reviews, providing feedback to build formal-friendly designs.
Contribute to the continuous improvement of formal verification processes, including automation scripting.
Maintain thorough documentation of formal verification activities, proofs, and coverage results.
What we’re looking for
4+ years of experience in digital hardware engineering (RTL Design, DV, or Architecture).
Strong knowledge of Computer Architecture core concepts and Digital Logic Design (DLD).
Proficiency in SystemVerilog (RTL or verification constructs).
Familiarity with processors such as RISC-V, ARM, or complex SoC architectures.
An adversarial, "what-if" mindset to uncover obscure corner cases.
Self-motivated, proactive, and able to work independently on complex abstract problems.
Bonus Points
Hands-on exposure to Formal Verification tools or writing SVAs.
Knowledge of common on-chip bus protocols (AXI, AHB, APB, CHI) and memory coherency.
Experience with scripting/automation (Python, TCL) or multi-agent AI frameworks to streamline verification workflows.
Why join 10xEngineers?
Opportunity to work on state-of-the-art formal verification projects with leading international clients.
Master a globally scarce, highly sought-after skill set in exhaustive mathematical proof.
Training resources on advanced formal techniques, SVA, and RISC-V to ramp up your skills.
Collaborative culture with direct mentorship from experienced formal verification leads.
Your path to Formal Verification doesn’t need to be linear. Our team includes engineers who started in RTL design, SystemVerilog simulation, or architecture and successfully transitioned into Formal Verification with us. If you’re curious, rigorous in your thinking, and strong in microarchitecture fundamentals, we’ll teach you the formal tools and methodologies to build the rest.