Senior CPU Design Engineer

Industry: Semiconductor / CPU / RISC-V

Job Summary

At 10xEngineers, we design and develop advanced semiconductor IP and processor technologies for global customers, with a strong focus on RISC-V, CPU subsystems, SoC infrastructure, and high-performance digital design.

We are looking for a Senior RTL / CPU Design Engineer who can take ownership of complex hardware blocks from microarchitecture through RTL implementation, integration, and design sign-off.

This role is suited for an engineer who enjoys understanding how a system works at the architectural level, making microarchitectural decisions, writing high-quality RTL, and solving difficult hardware problems rather than simply implementing predefined designs.

You will work closely with architects, verification engineers, and other design engineers to develop production-quality semiconductor IP.

What you'll do

• Own the microarchitecture and RTL implementation of complex CPU, processor-subsystem, or SoC IP blocks.

• Translate architectural specifications into clear, efficient, and synthesizable microarchitectures.

• Develop high-quality SystemVerilog RTL with careful consideration of correctness, performance, area, timing, and power.

• Work on processor and SoC components such as:

  • CPU pipelines and execution units

  • Load/store units and memory subsystems

  • Caches and cache controllers

  • MMU, TLB, and address translation

  • Interrupt and debug infrastructure

  • RISC-V privileged and ISA-related features

  • Interconnect and coherence-related components

  • IOMMU and I/O virtualization infrastructure

  • High-performance SoC interfaces and data paths

• Analyze architectural and microarchitectural trade-offs and propose implementation approaches.

• Debug complex RTL and simulation failures using waveforms, assertions, logs, and targeted test cases.

• Work closely with verification engineers to identify root causes and resolve functional issues.

• Participate in design reviews, microarchitecture reviews, RTL reviews, and sign-off activities.

• Review existing RTL and contribute to improving design quality, performance, maintainability, and scalability.

• Develop and maintain design documentation, specifications, and implementation plans.

• Contribute to lint, CDC, synthesis, timing, and other design-quality/sign-off activities.

• Develop scripts and automation in Python, Tcl, Bash, or similar languages to improve design and debug workflows.

• Mentor junior and mid-level engineers and provide technical guidance on RTL and microarchitecture.

• Collaborate with distributed teams and customers on technically challenging semiconductor projects.

What we're looking for

• 2+ years of hands-on experience in RTL, CPU, SoC, or digital hardware design.

• Strong fundamentals in:

  • Computer Architecture

  • Digital Logic Design

  • Microarchitecture

  • RTL Design

• Strong hands-on experience with SystemVerilog and/or Verilog.

• Experience taking a hardware block from specification to RTL implementation and integration.

• Ability to reason about complex hardware behavior across multiple cycles, interfaces, and pipeline stages.

• Good understanding of concepts such as:

  • pipelining and pipeline control

  • arbitration and scheduling

  • FIFOs and buffering

  • caches and memory hierarchy

  • virtual memory and address translation

  • interrupts and exceptions

  • performance, latency, throughput, and backpressure

  • on-chip communication and protocols

• Experience debugging RTL using simulation and waveform-based analysis.

• Familiarity with hardware design quality and sign-off flows such as lint, CDC, synthesis, timing, and coverage.

• Experience working with hardware specifications and identifying ambiguities, corner cases, and implementation gaps.

• Strong problem-solving skills and the ability to independently drive technical issues to closure.

• Experience with scripting/programming in Python, Tcl, Bash, C/C++, or similar languages.

Engineering Skills That Matter

Beyond individual technical skills, we value engineers who can:

• Own problems end-to-end rather than waiting for detailed instructions.

• Understand the difference between an architectural requirement and an implementation choice.

• Identify corner cases before they become verification bugs.

• Challenge unclear or incomplete specifications and ask the right architectural questions.

• Make engineering trade-offs based on performance, area, timing, complexity, and verification effort.

• Write RTL that is understandable, maintainable, and robust.

• Work effectively with verification engineers and treat design and verification as a shared responsibility.

• Review other engineers' designs and provide technically sound feedback.

• Communicate complex technical ideas clearly through design documents, diagrams, and discussions.

• Mentor other engineers and contribute to raising the overall technical quality of the team.

What You Can Expect

You will work on real semiconductor projects involving RISC-V processors, CPU subsystems, SoC infrastructure, and advanced IP, with opportunities to work across architecture, microarchitecture, RTL, verification, and physical implementation boundaries.

The role provides significant technical ownership. Senior engineers are expected not only to implement designs, but also to shape the microarchitecture, identify technical risks, review designs, mentor engineers, and drive complex problems to completion.